Automatic Test Equipment (ATE) for digital Integrated Circuits (ICs) is required to provide a flow of digital data that is used to generate the input signals required to stimulate the IC under test and to provide the expected response data that is compared to the output data generated by the IC. This digital data is referred to as “test pattern data.”
Prior Art FIG. 1 depicts a simplified diagram of an ATE system 100 and an integrated circuit under test 115. Test pattern data is read from the tester's pattern memory 105 in the form of “vectors,” where each vector contains a set of individual “pin-vector” data. Each individual “pin-vector” may be comprised of 1, 2, 3, or possibly more bits which represents a potential new state of data at a specific signal pin. Automatic Test Equipment is configured with some finite number of signal “pins” (Pin 1, Pin 2 . . . Pin n), where each signal pin is to be connected to a physical signal pin of the integrated circuit under test. The typical number of pins found on state of the art ATE is in the range of 256 to 1024 pins. For each pin implemented in the ATE, there would be a memory for storing the test pattern and signal generation/comparison circuitry 110(1) to 110(n) for generating the appropriate waveform as specified by the pin-vector data and for also comparing data received from the IC against the pin-vector data.
Depending upon the complexity of the IC, the amount of test pattern data required to sufficiently test a digital IC can be from a few hundred-thousands to several million vectors. Each digital signal pin of an IC is typically categorized as one of three (3) types: an “input” pin is capable of only “receiving” signals from the IC tester; an “output” pin is capable only of “outputting” signals to the IC tester; and a “bi-directional” pin is capable of switching back and forth between being an input and an output pin from one data cycle to another.
There are two general methods used for the application of test pattern data to the IC. The first method requires that test pattern data be applied in parallel to all signal pins of the IC in each and every vector. This method is required to “functionally” test the device. The second method utilizes additional logic circuitry added to the IC to enable the test pattern data to be applied to a smaller subset of the signal pins, with the data being “serially” redistributed within the IC itself to all of the internal logic functions for testing. This addition of logic is referred to as adding Design For Test (or DFT) and the method used to subsequently test the IC is referred to as “structural” testing.
Parallel test pattern vectors are provided to all pins of the IC at a specific programmed rate which is determined by the IC's specified operating rate against which it is being tested. During the test of a digital integrated circuit, these “parallel” test patterns require that unique pattern data be applied to all signal pins of the device on each data cycle.
Conversely, serial test patterns are serially shifted into an IC's internal memory elements through a small set of external serial data input pins called “scan-in pins.” After the IC's internal shift register memory has been fully loaded with the desired pattern, the internal test pattern data is then applied to the internal logic and the resultant output of the logic being tested is captured back into the IC's serial shift register memory. The resultant data is then serially shifted out through a small set of external serial data output pins called “scan-out pins.” The data is compared against the expected results as it is being shifted out, and any variation between shifted data and expected results indicates a defective IC. To completely test an IC, this process is typically repeated several hundreds or thousands of times.
Importantly, in between each serial shift-in/shift-out sequence, a small sequence of parallel vectors may be applied to all of the IC pins.
Prior Art FIG. 2 depicts an example of the interleaving of parallel and serial test vectors. Each line in the figure represents the vector data for one test cycle. Each column represents the activities on a single signal pin of the IC. Each individual character represents a “pin-vector,” which specifies the test activity that is to occur on that signal pin during that cycle. In the example given, the following pin-vector characters would specify the following actions: “0”—apply a low input data level to the IC pin; “1”—apply a high input data level to the IC pin; “L”—test the output of the IC pin for a valid low data level; “H”—test the output of the IC pin for a valid high data level; and “X”—allow the IC to output data, but do not test its data state.
In FIG. 2, sequences 200, 210 and 220 are parallel vector sequences, where unique data is applied to all signal pins for functional testing. Interleaved with the parallel vector sequences are serial scan vector sequences 205 and 215 for structural testing. In the serial scan vector sequences, data may be applied or tested on a small subset of the pins. During the cycles in which a serial data pattern is being applied to the serial pins, the values applied to the non-serial pins are fixed.
In the example of FIG. 2, there are thirty-two (32) total signal pins, and four (4) serial scan pins (pins 9, 12, 24, and 30). In the figure, the serial pin-vectors are indicated by underlined bold characters. In this example, pin 30 and pin 12 are scan-in pins while pin 24 and pin 9 are scan-out pins.
The ratio of the number of serial vectors to the parallel vectors required to test an IC may be several hundred to one. The number of serial pins used as a ratio to the total number of parallel signal pins varies with the IC design. A representative set of test pattern parameters for structurally testing an IC is shown in Table 1.
TABLE 1Total number of signal pins384Total number of serial pins.16Total number of parallel vectors40,000(on all pins)″Total number of serial vectors20,000,000(on serial pins)″Total number of pin-vectors required.335,360,000(384 × 40,000 + 16 × 20,000,000)
Design approaches used by automatic test equipment to generate, store, and deliver the above type of data pattern sequences has generally relied on one of three different implementations.
The first conventional implementation utilizes the basic pattern memory 105 depicted in FIG. 1. The architecture of FIG. 1 requires that unique pin-vector pattern data be stored for every pin (both parallel and serial pins) for every cycle (both parallel and serial vector cycles). This means that pattern data on the non-serial data pins is replicated for every serial vector as shown in region 205 of FIG. 2. The advantage to this approach is that it does not require any incremental change to the basic parallel tester design to implement. However, the overwhelming constraint is the enormous amount of pattern memory required for typical scan based test applications. Most of the memory is used to store duplicate pattern data. Based on the parameters given in Table 1, system 100 would require a pattern memory capable of holding almost eight billion pin vectors, which is more than twenty times greater than what would be required in the alternative implementations described below.
The second conventional implementation shown in FIG. 3 and uses two separate memories, e.g., a first memory 305 that is used to store the parallel vector data, and a second memory 310 for storing serial vector data. This implementation has multiplexer 315 and multiplexer 316. Memory 305 stores the parallel vector data for every tester channel and memory 310 stores the serial vector data patterns. Serial vector memory 310 is organized with deeper depth but narrower width than memory 305. As an example, for a 512 pin tester memory 305 might have 4 million locations with 512 pin-vectors (one per pin) stored at each location. Memory 310 might have 256 million locations with each location storing 16-pin-vectors. Memory 310 would also typically be software reconfigurable to provide longer serial vector sequences at the expense of fewer serial data channels (e.g., 8 channels by 512M deep).
Each individual tester channel would be implemented with a 16 to 1 data multiplexer 315 which is controlled by register 320. Register 325 would be set for those pins for which a serial data pattern is generated during scan pattern sequences. During the execution of serial vector sequences (as enabled by the Serial Enable signal from memory), the parallel vector memory would remain on the last parallel vector executed.
While this method provides deeper serial depth and better memory utilization, it has two major disadvantages. The first disadvantage is that the distribution of the serial memory outputs to all of the other tester pins is typically very complex and expensive (the distribution cost may be more than the cost of the memory itself). The second disadvantage is that the maximum serial memory width is limited in practice to about 16 serial channels because of the complexity of the distribution and multiplexer logic. The limitation of providing only 16 serial channels means only 16 scan chains can be supported for any serial scan cycle.
A third conventional implementation is depicted in Prior Art FIG. 4. This implementation utilizes a single memory 405 to store both parallel (functional) and serial (structural) vector data. The output of memory 405 is wide enough to provide parallel data for all tester pins. The pin population is further divided into smaller fixed length pin segments (represented as pins J through J+n in FIG. 4). The vector pattern segment from memory 405 (DO–Dn) for each segment goes to the inputs of parallel-in/parallel-out shift register 410. One of these shift registers 410 is provided for each such segment. Only one segment is shown.
Each parallel output of shift register 410 (QO–Qn) is connected to respective multiplexer 415 of each pin circuitry 402(j). Only the connection of Q0 is shown. Multiplexer 415 is controlled by the output of AND gate 435. During parallel vector sequences the data passes through shift register 410 into register 420 on each clock cycle signal 430, and subsequently to the pin logic through the register 420 output.
Conversely, during a serial data sequence, memory pointer 440 holds the present memory address while the data loaded into shift register 410 is serially shifted. Each pin may be individually programmed to either output the data from the shift register 410 during these shift cycles, or to maintain the data last output prior to a shift signal going true. This is determined by the state programmed into each pin's data hold register 425.
Depending upon the number of serial pins located in any segment, the data in the shift register 410 is serially shifted such that the data appears at the pin(s) assigned as serial data pins. While this approach has advantages over the previous implementation, its major disadvantage is that it severely limits the assignment of serial scan-in pins within the pin segment to evenly distributed pins. For example, if the pin segment has 16 pins (n=16) and there are two serial scan-in pins required within a sixteen pin segment, each pattern vector word could then contain two serial vector sequences of only 8 vectors each. However, the two serial pins would have to be selected so that they are exactly 8 pins apart. In practice the outputs of register 410 are essentially dedicated to a particular pin as the scan-in pin so that unique data can be provided for serial scan-in. This is often a major constraint on the use of this implementation.